Semiconductor heterostructure and method for forming same
US8084784B2 · kind B2 · utility
3Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2010 |
| Grant date | Dec 27, 2011 |
| Priority date | — |
| Expiry date | Jun 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.