Method of forming source and drain of a field-effect-transistor and structure thereof

US8084788B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Judson R. Holt · Wappingers Falls, US
• Abhishek Dube · Fishkill, US
• Eric C. Harley · Lagrangeville, US
• Shwu-Jen Jeng · Wappingers Falls, US
• Jeremy J. Kempisty · Beacon, US
• Hasan M. Nayfeh · Hopewell Junction, US
• Keith H. Tabakman · Newburgh, US

Key dates

• Filing date: Oct 10, 2008
• Grant date: Dec 27, 2011
• Expiry date: Dec 14, 2028

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.