Method of forming self-aligned low resistance contact layer
US8088665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2008 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | May 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/02636
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.