Structure and method for determining a defect in integrated circuit manufacturing process
US8089297B2 · kind B2 · utility
88Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2008 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Sep 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/24
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.