Method and apparatus for characterizing an integrated circuit manufacturing process
US8091063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2008 |
| Grant date | Jan 3, 2012 |
| Priority date | — |
| Expiry date | Oct 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A system that characterizes an integrated circuit manufacturing process is presented. During operation, the system receives a layout which includes a plurality of test structures for semiconductor devices, wherein each test structure varies one or more design variables. The system then fabricates a plurality of wafers based on the layout, wherein each wafer in the plurality of wafers is fabricated using one of a plurality of process settings. Next, the system obtains performance characteristics for the plurality of test structures on the plurality of wafers. The system then generates a process model that is based on at least the effect that values for the one or more design variables and the plurality of process settings have on the performance characteristics of the plurality of test structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.