Chip package and manufacturing method thereof
US8093690B2 · kind B2 · utility
53Cited by
48References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 31, 2009 |
| Grant date | Jan 10, 2012 |
| Priority date | — |
| Expiry date | Sep 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0415
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.