Patent · US Active

Memory system and method

US8095747B2 · kind B2 · utility

2Cited by

1References

18Claims

0Family size

Assignee

Cypress Semiconductor Corporation · US

Inventors

Bruce Barbara · Discovery Bay, US
Gabriel Li · San Francisco, US
Thinh Tran · Palo Alto, US
Joseph Tzou · Belmont, US

Key dates

Filing date	Sep 26, 2008
Grant date	Jan 10, 2012
Priority date	—
Expiry date	Aug 19, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/28
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, an apparatus includes a memory controller configured to control first and second memory components. A point-to-point data bus configured to pass data between the memory controller and the memory components may include a direct connection from each memory component to the memory controller. A daisy chained address bus configured to pass commands between the memory controller and the memory components may include a direct connection from the first memory component to the memory controller and a daisy chain connection from the first memory component to the second memory component.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.