Patent · US Active

Using electric-field directed post-exposure bake for double-patterning (D-P)

US8097402B2 · kind B2 · utility

19Cited by

6References

20Claims

0Family size

Assignee

TOKYO ELECTRON LIMITED · JP

Inventors

Steven Scheer · Austin, US
Mark H. Somervell · Richardson, US

Key dates

Filing date	Mar 31, 2009
Grant date	Jan 17, 2012
Priority date	—
Expiry date	Jul 24, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/0337
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

The invention provides a method of processing a substrate using Double-Patterning (D-P) processing sequences and Electric-Field Enhanced Layers (E-FELs). The D-P processing sequences and E-FELs can be used to create lines, trenches, vias, spacers, contacts, and gate structures using a minimum number of etch processes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.