Self-checking and self-correcting internal configuration port circuitry
US8099625B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2009 |
| Grant date | Jan 17, 2012 |
| Priority date | — |
| Expiry date | Jan 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for self-checking and self-correcting memory states of a programmable resource is described. Programmable resource of an integrated circuit has a first core and a second core instantiated therein. A first internal configuration port and a second internal configuration port of the integrated circuit are respectively connected to the first core and the second core. The second core is coupled to the first core for monitoring operation of the first core with the second core, and the second core is configured to obtain control responsive to a failure of the first core or the first internal configuration port for a self-correcting mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.