Method of forming a FET having ultra-low on-resistance and low gate charge
US8101484B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2010 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jul 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/516
Abstract
In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.