Stacked integrated circuit and package system and method for manufacturing thereof
US8102043B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2011 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jan 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a stacked integrated circuit and package system includes: attaching a high temperature resistant layer on a top substrate; mounting a first top integrated circuit on the high temperature resistant layer; mounting a second top integrated circuit on the first top integrated circuit; molding an encapsulant over the first top integrated circuit, the second top integrated circuit and the top substrate; mounting a third top integrated circuit over the first top integrated circuit on a surface opposite the second top integrated circuit; mounting a fourth top integrated circuit on the third top integrated circuit; molding an encapsulant over the third top integrated circuit, the fourth top integrated circuit and the top substrate; forming top electrical connectors on a lower surface of the top substrate; and mounting a bottom package to the top electrical connectors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.