Method of testing for a leakage current between bit lines of nonvolatile memory device
US8102717B2 · kind B2 · utility
3Cited by
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10Claims
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Key dates
| Filing date | Dec 30, 2009 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Apr 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of testing for a leakage current between bit lines of a nonvolatile memory device includes providing the nonvolatile memory device with a page buffer having first and second bit lines coupled thereto, precharging the first bit line to a first voltage, supplying a second voltage to the second bit line, floating the second bit line and evaluating the second bit line for a set time period, and detecting a voltage level of the second bit line and outputting a test result of testing for the leakage current between the first and second bit lines by the page buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.