Circuit for and method of repairing defective memory
US8103919B1 · kind B1 · utility
4Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2009 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Oct 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for repairing defective memory of an integrated circuit is disclosed. The circuit includes blocks of memory; and interconnect elements providing data to each of the blocks of memory, where the interconnect elements enable coupling together the signals for programming the blocks of memory. The circuit also includes a directory of locations for defective memory cells of blocks of memory, where the directory of locations is common to the blocks of memory for storing locations of defective memory cells of the blocks of memory. Methods of repairing defective memory of an integrated circuit are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.