Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuits
US8103997B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2009 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Dec 17, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for converting interconnect parasitics of an interconnect network into slew dependent pin capacitances utilizes charge matching between predetermined voltage thresholds. During timing abstraction of a macro, parasitics of interconnects connected to the primary inputs are represented as slew dependent pin capacitances in an abstract model being created. Interconnect model order reduction is employed to speed the process. The generated abstract is subsequently used in place of each occurrence of the macro during chip level hierarchical static timing analysis, leading to an enhanced accuracy of the timing analysis of the logic components driving the abstracts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.