Regular local clock buffer placement and latch clustering by iterative optimization
US8104014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2008 |
| Grant date | Jan 24, 2012 |
| Priority date | — |
| Expiry date | Jan 22, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.