Methods of fabricating transistors including self-aligned gate electrodes and source/drain regions
US8105889B2 · kind B2 · utility
1Cited by
19References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Oct 16, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/815
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming Group III-nitride transistor device include forming a protective layer on a Group III-nitride semiconductor layer, forming a via hole through the protective layer to expose a portion of the Group III-nitride semiconductor layer, and forming a masking gate on the protective layer. The masking gate includes an upper portion having a width that is larger than a width of the via hole and having a lower portion extending into the via hole. The methods further include implanting source/drain regions in the Group III-nitride semiconductor layer using the masking gate as an implant mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.