Semiconductor device package having features formed by stamping
US8106493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2010 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Oct 13, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49124
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.