Integrated circuit packaging system with a dual substrate package and method of manufacture thereof
US8106499B2 · kind B2 · utility
13Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2009 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Jan 27, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a base substrate having a base conductive material on opposite sides of the base substrate; connecting an internal interconnect having a substantially spherical shape on the base substrate; forming a top substrate having a top conductive material on opposite sides of the top substrate with an upper component thereon facing the base substrate; and attaching the top substrate on the internal interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.