Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces
US8108744B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2007 |
| Grant date | Jan 31, 2012 |
| Priority date | — |
| Expiry date | Aug 20, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.