Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packages
US8110439B2 · kind B2 · utility
1Cited by
17References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2009 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.