Planar SRFET using no additional masks and layout method
US8110869B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 2007 |
| Grant date | Feb 7, 2012 |
| Priority date | — |
| Expiry date | Jul 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/64
Abstract
A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.