Patent · US Active

Semiconductor wafer with a heteroepitaxial layer and a method for producing the wafer

US8115195B2 · kind B2 · utility

1Cited by

4References

2Claims

0Family size

Assignee

Siltronic AG · DE

Inventors

Peter Storck · Mehring, DE
Martin Vorderwestner · Unterreit, DE

Key dates

Filing date	Mar 18, 2009
Grant date	Feb 14, 2012
Priority date	—
Expiry date	Nov 20, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/0251
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.