Integrated circuit packaging system with interconnect and method of manufacture thereof
US8115293B2 · kind B2 · utility
17Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2009 |
| Grant date | Feb 14, 2012 |
| Priority date | — |
| Expiry date | Aug 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; mounting a first exposed interconnect on the outer pad; forming a first encapsulation over the stack substrate, the first exposed interconnect partially exposed and the inner pad partially exposed in a recess of the first encapsulation; and mounting a second exposed interconnect on the inner pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.