Methods of forming integrated circuit capacitors having sidewall supports and capacitors formed thereby
US8119476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2010 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Oct 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/716
Abstract
In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.