Semiconductor device with improved trenches
US8120075B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2010 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Nov 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device exhibiting enhanced carrier mobility within a channel region of the semiconductor device is disclosed. The semiconductor device includes a gate stack having first and second sidewall spacers, where the gate stack is implemented above the channel region of the semiconductor device. The semiconductor device further includes first and second trenches formed adjacent to the gate stack, where the first and second trenches are conically shaped to be wider at a top portion of each trench as compared to a width of each trench below the top portion of each trench. The semiconductor device further includes strained silicon alloy formed within the first and second trenches, where a stress force exerted on the channel region of the semiconductor device is maximized at a surface of the semiconductor device below the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.