Methods and materials useful for chip stacking, chip and wafer bonding
US8120168B2 · kind B2 · utility
3Cited by
7References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2007 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Nov 15, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.