Integrated package circuit with stiffener
US8120170B2 · kind B2 · utility
8Cited by
18References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2008 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Apr 28, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.