Semiconductor device having a conductive bump
US8120176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2010 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Sep 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.