Measurement methodology and array structure for statistical stress and test of reliabilty structures

US8120356B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Kanak B. Agarwal · Austin, US
• Nazmul Habib · South Burlington, US
• Jerry D. Hayes · Georgetown, US
• John G. Massey · Jericho, US
• Alvin W. Strong · South Burlington, US

Key dates

• Filing date: Jun 11, 2009
• Grant date: Feb 21, 2012
• Expiry date: Aug 18, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318511
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

System and method for obtaining statistics in a fast and simplified manner at the wafer level while using wafer-level test equipment. The system and method performs a parallel stress of all of the DUTs on a given chip to keep the stress time short, and then allows each DUT on that chip to be tested individually while keeping the other DUTs on that chip under stress to avoid any relaxation. In one application, the obtained statistics enable analysis of Negative Temperature Bias Instability (NTBI) phenomena of transistor devices. Although obtaining statistics may be more crucial for NBTI because of its known behavior as the device narrows, the structure and methodology, with minor appropriate adjustments, could be used for stressing multiple DUTs for many technology reliability mechanisms.