NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same
US8120959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2009 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Apr 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5644
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile memory device includes a nonvolatile memory array including a plurality of charge retaining transistors arranged in rows and columns. The device has a plurality source lines formed in parallel with the bit lines associated with each column. Row decode/driver circuits are connected to blocks of the charge retaining transistors for controlling the application of the necessary read, program, and erase signals. Erase count registers, each of the erase count registers associated with one block of the array of the charge retaining transistors for storing an erase count for the associated block for determining whether a refresh operation is to be executed. Groupings on each column of the array of charge retaining transistors are connected as NAND series strings where each NAND string has a select gating charge retaining transistor connected to the top charge retaining transistor for connecting the NAND series string to the bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.