Memory having negative voltage write assist circuit and method therefor
US8120975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2009 |
| Grant date | Feb 21, 2012 |
| Priority date | — |
| Expiry date | Aug 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of writing data to a selected column of a memory includes selecting a first column. The data writing is initiated by applying a logic high to a first bit line of the first column and a first potential to a second bit line of the first column that is lower than the logic high. The first potential is removed and a second potential is applied to the second bit line. The second potential is less than the first potential. The first potential may be ground, and the second potential may be a negative voltage. Reducing the write voltage for the bit line that is receiving a logic low improves its ability to be written. By first bringing the logic low to the first potential, which may be ground, and then further reducing the applied voltage, the requirements on the source of the second potential are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.