Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuits

US8122404B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Debjit Sinha · Wappingers Falls, US
• Adil Bhanji · Wappingers Falls, US
• Barry Lee Dorfman · Austin, US
• Kerim Kalafala · Rhinebeck, US
• Natesan Venkateswaran · Hopewell Junction, US
• Chandramouli Visweswariah · Croton-on-Hudson, US

Key dates

• Filing date: Feb 19, 2009
• Grant date: Feb 21, 2012
• Expiry date: Jul 12, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3312
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for performing a hierarchical statistical timing analysis of an integrated circuit (IC) chip design by abstracting one or more macros of the design. The method includes performing a statistical static timing analysis of at least one macro; performing a statistical abstraction of the macro to obtain a statistical abstract model of the macro timing characteristics; applying the statistical abstract model as the timing model for each occurrence of the macro leading to a simplified IC chip design; and performing a hierarchical statistical timing analysis of the simplified chip design. The method achieves a context aware statistical abstraction, where a generated statistical abstract model is instantiated for each macro of the chip during statistical static timing analysis at the chip level, providing a compressed and pruned statistical timing abstraction and reducing the model-size during the statistical abstraction.