Method for enhancing tensile stress and source/drain activation using Si:C
US8124487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2008 |
| Grant date | Feb 28, 2012 |
| Priority date | — |
| Expiry date | May 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing a series of ion implantation steps at predetermined implant energies to implant carbon ions deep within the semiconductor structure to create a strain layer. The strain layer is annealed using a millisecond anneal process. Subsequent ion implantation steps are used to dope the source/drain region, and the source/drain extension with phosphorus ions, so that the doped regions remain above the strain layer. A second millisecond anneal step activates the source/drain region and the source/drain extension. The strain layer enhances carrier mobility within a channel region of the semiconductor structure, while also preventing diffusion of P within the structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.