Power lead-on-chip ball grid array package
US8129226B2 · kind B2 · utility
4Cited by
13References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2007 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | May 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A packaging assembly (30), such as a ball grid array package, is formed which distributes power across an interior region of an integrated circuit die (52) by using an encapsulated patterned leadframe conductor (59) that is disposed over the die (52) and bonded to a plurality of bonding pads (45) formed in a BGA carrier substrate (42) and in the interior die region, thereby electrically coupling the interior die region to an externally provided reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.