Fabrication of field-effect transistor with vertical body-material dopant profile tailored to alleviate punchthrough and reduce current leakage
US8129262B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Nov 9, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
Fabrication of an insulated-gate field-effect transistor (110) entails separately introducing three body-material dopants, typically through an opening in a mask, into body material (50) of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode (74) is subsequently defined after which a pair of source/drain zones (60 and 62), each having a main portion (60M or 80M) and a more lightly doped lateral extension (60E or 62E), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (100 and 102) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.