Work function engineering for eDRAM MOSFETs

US8129797B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Xiangdong Chen · Irvine, US
• Herbert L. Ho · New Windsor, US
• Geng Wang · Stormville, US

Key dates

• Filing date: Jun 18, 2008
• Grant date: Mar 6, 2012
• Expiry date: Sep 20, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.