Tracking effective addresses in an out-of-order processor

US8131976B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Richard W. Doing · Raleigh, US
• Susan E. Eisen · Round Rock, US
• David S. Levitan · Austin, US
• Kevin N. Magill · Durham, US
• Brian R. Mestan · Austin, US
• Balaram Sinharoy · Poughkeepsie, US
• Benjamin W. Stolt · Austin, US
• Jeffrey R. Summers · Raleigh, US
• Albert J. Van Norstrand, Jr. · Round Rock, US

Key dates

• Filing date: Apr 13, 2009
• Grant date: Mar 6, 2012
• Expiry date: Feb 25, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/3861
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective address table logic in the data processing system, an entry in an effective address table (EAT) data structure with the fetched instruction. The mechanisms further comprise logic for associating an effective address tag (eatag) with the fetched instruction, the eatag comprising a base eatag that points to the entry in the EAT and an eatag offset. Moreover, the mechanisms comprise logic for processing the instruction through the processor pipeline by processing the eatag.