Systems and methods to efficiently schedule commands at a memory controller
US8132048B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2009 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Apr 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/141
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods to respond to schedule commands at a memory controller are disclosed. A transmission error between a first memory controller port and a first redrive device may be detected. A first corrective action may be initiated at the first memory controller port in response to the detection of the transmission error. A particular method may include determining that a second memory controller port initiated a second corrective action. Incoming read commands may be distributed based on a comparison of the first corrective action and the second corrective action.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.