Dynamic critical path detector for digital logic circuit paths
US8132136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2007 |
| Grant date | Mar 6, 2012 |
| Priority date | — |
| Expiry date | Jul 11, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method for correcting timing failures in an integrated circuit and device for monitoring an integrated circuit. The method includes placing a first and second latch near a critical path. The first latch has an input comprising a data value on the critical path. The method further includes generating a delayed data value from the data value, latching the delayed data value in the second latch, comparing the data value with the delayed data value to determine whether the critical path comprises a timing failure condition, and executing a predetermined corrective measure for the critical path. The invention is also directed to a design structure on which a circuit resides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.