Packaged system of semiconductor chips having a semiconductor interposer
US8133761B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2009 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Jun 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor system (200) of one or more semiconductor interposers (201) with a certain dimension (210), conductive vias (212) extending from the first to the second surface, with terminals and attached non-reflow metal studs (215) at the ends of the vias. A semiconducting interposer surface may include discrete electronic components or an integrated circuit. One or more semiconductor chips (202, 203) have a dimension (220, 230) narrower than the interposer dimension, and an active surface with terminals and non-reflow metal studs (224, 234). One chip is flip-attached to the first interposer surface, and another chip to the second interposer surface, so that the interposer dimension projects over the chip dimension. An insulating substrate (204) has terminals and reflow bodies (242) to connect to the studs of the projecting interposer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.