Method and system for modifying patterned photoresist using multi-step ion implantation
US8133804B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2010 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Oct 1, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/31796
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.