Method for testing noise immunity of an integrated circuit and a device having noise immunity testing capabilities
US8134384B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2006 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Dec 19, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing a noise immunity of an integrated circuit; the method includes: determining a value of a power supply noise regardless of a relationship between the power supply noise value and a phase sensitive signal edge position resulting from an introduction of the power supply noise; receiving, by the integrated circuit, a phase sensitive signal; introducing jitter to the phase sensitive signal by a circuit adapted to generate a substantially continuous range of power supply noise such as to alter edges position of the phase sensitive signal; providing the jittered phase sensitive signal to at least one tested component of the integrated circuit; and evaluating at least one output signal generated by the at least tested component to determine the noise immunity of the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.