Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs
US8136010B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2007 |
| Grant date | Mar 13, 2012 |
| Priority date | — |
| Expiry date | Jan 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6575
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.