Transistor device comprising an asymmetric embedded semiconductor alloy
US8138050B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Feb 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Transistor characteristics may be adjusted on the basis of asymmetrically formed cavities in the drain and source areas so as to maintain a strain-inducing mechanism while at the same time providing the possibility of obtaining asymmetric configuration of the drain and source areas while avoiding highly complex implantation processes. For this purpose, the removal rate during a corresponding cavity etch process may be asymmetrically modified on the basis of a tilted ion implantation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.