Casey Scott
13Patents
4h-index
13Co-inventors
49Inventor score
Filing activity: Jul 17, 2007 → May 18, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7811876B2 | Reduction of memory instability by local adaptation of re-crystallization conditions in a cache area of a semiconductor device | Electricity | 9 | Active |
| US8212184B2 | Cold temperature control in a semiconductor device | Electricity | 9 | Active |
| US8093634B2 | In situ formed drain and source regions in a silicon/germanium containing transistor device | Electricity | 7 | Active |
| US8183100B2 | Transistor with embedded SI/GE material having enhanced across-substrate uniformity | Electricity | 4 | Active |
| US8138050B2 | Transistor device comprising an asymmetric embedded semiconductor alloy | Electricity | 4 | Active |
| US7713763B2 | Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions | Electricity | 3 | Active |
| US8227266B2 | Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions | Electricity | 3 | Active |
| US8373244B2 | Temperature monitoring in a semiconductor device by thermocouples distributed in the contact structure | Electricity | 2 | Active |
| US9450073B2 | SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto | Electricity | 2 | Active |
| US7897451B2 | Method for creating tensile strain by selectively applying stress memorization techniques to NMOS transistors | Electricity | 1 | Active |
| US8530894B2 | Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions | Electricity | 0 | Active |
| US8652913B2 | Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss | Electricity | 0 | Active |
| US8334569B2 | Transistor with embedded Si/Ge material having enhanced across-substrate uniformity | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.