Method of forming source and drain of field-effect-transistor and structure thereof
US8138053B2 · kind B2 · utility
9Cited by
3References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 15, 2007 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Sep 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
Embodiments of the invention provide a method of forming a field-effect-transistor (FET). The method includes implanting one or more n-type dopants to create one or more implanted regions with at least a portion of the implanted regions being designated as regions for forming source and drain extensions of the FET; activating the implanted regions; etching with a chlorine based etchant to create openings in the implanted regions, and forming the source and drain extensions by exptaxially growing embedded silicon germanium in the openings. Structure of a semiconductor field-effect-transistor made thereof is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.