Method of manufacturing an integrated circuit
US8138087B2 · kind B2 · utility
6Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2007 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Aug 15, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit is provided that comprises a substrate of silicon and an interconnect in a through-hole extending from the first to the second side of the substrate. The interconnect is coupled to a metallization layer on the first side of the substrate and is provided on an amorphous silicon layer that is present at a side wall of the through-hole, and particularly at an edge thereof adjacent to the first side of the substrate. The interconnect comprises a metal stack of nickel and silver. A preferred way of forming the amorphous silicon layer is a sputter etching technique.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.