Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby
US8138524B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2006 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Jan 12, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a substrate of semiconductor material having a first conductivity type, source and drain regions formed in the substrate, a block of conductive material disposed over and electrically connected to the source, and a floating gate having a first portion disposed over and insulated from the source region and a second portion disposed over and insulated from the channel region. The floating gate first portion includes a sloped upper surface and a side surface that meet at an acute edge. An electrically conductive control gate is disposed over and insulated from the channel region for controlling a conductivity thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.