Erase degradation reduction in non-volatile memory
US8139421B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2010 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Oct 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/344
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for erasing a memory device and memory systems are provided, such as those including a non-volatile memory device is erased by using an intermediate erase step prior to a normal erase step. The intermediate erase step is comprised of an erase pulse voltage, applied to the semiconductor well of the selected memory block of memory cells, while edge rows of memory cells are biased at a low positive voltage (e.g., 0.2-2V). An erase verify operation is then performed. If the selected memory block is not erased, a normal memory erase step is then performed in which the same erase pulse voltage is used but all of the rows are biased at ground potential as in a normal erase step. If the memory block is still fails the erase verify operation, the erase pulse voltage is increased and the process repeated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.