Power-on initialization and test for a cascade interconnect memory system

US8139430B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Peter Buchmann · Thalwil, CH
• Frank D. Ferraiolo · New Windsor, US
• Kevin C. Gower · Lagrangeville, US
• Robert J. Reese · Austin, US
• Eric E. Retter · Austin, US
• Martin Schmatz · Thalwil, CH
• Michael B. Spear · Round Rock, US
• Peter Matthew Thomsen · Austin, US
• Michael R. Trombley · Rochester, US

Key dates

• Filing date: Jul 1, 2008
• Grant date: Mar 20, 2012
• Expiry date: Feb 14, 2030

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D10/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.